This invention is related to a method for manufacturing a semiconductor device and more particularly to a method for manufacturing a semiconductor device which improves an isolation technique.
To date, the pn junction isolation process and selective oxidation isolation process have generally been applied in manufacturing a semiconductor device, particularly a bipolar IC. For reference, the pn junction isolation and selective oxidation isolation jointly applied in manufacturing a vertical npn type bipolar transistor will now be described.
First, as shown in FIG. 1A, an n.sup.+ type layer 2 is selectively embedded in a p type silicon substrate 1. Thereafter, an n type silicon layer 3 is deposited by epitaxial growth on said n.sup.+ type layer 2. A silicon oxide film 4 is mounted on said n type silicon layer 3 with a thickness of about 1,000 .ANG. A. An oxidation-resistive silicon nitride film 5 is formed on said silicon oxide film 4 with a thickness of about 1,000 .ANG. A. Thereafter, as shown in FIG. 1B, the silicon oxide film 4 and silicon nitride film 5 are photolithographically patterned to provide silicon oxide film patterns 4a, 4b and silicon nitride film patterns 5a, 5b. As shown in FIG. 1C, the n type silicon layer 3 is etched to about 5,000 .ANG. with the silicon oxide film patterns 4a, 4b, and silicon nitride film patterns 5a, 5b used as a mask. An impurity of boron is ion-implanted in the n type silicon layer 3 with the above-mentioned patterns 4a, 4b, 5a, 5b as a mask, thereby producing p type regions 6a, 6b in the n type silicon layer 3. Then as seen from FIG. 1D, silicon oxide films 7a, 7b, 7c are selectively formed by thermal oxidation with a thickness of about 1 micron in steam or a wet atmosphere on those portions of the surface of the silicon layer 3 which are not covered with the silicon nitride film patterns 5a, 5b.
The silicon nitride film patterns 5a, 5b are etched off, for example, by hot phosphoric acid. A p type impurity of, for example, boron is ion-implanted through the silicon oxide film pattern 4a in that portion of the silicon layer 3 which lies beneath the silicon nitride film pattern 5a, thereby producing a base region 8 (FIG. 1E). An n type impurity of, for example, arsenic is ion-implanted in one section of the base region 8 and that portion of the silicon layer 3 which is interposed between the silicon oxide films 7b, 7c, thereby providing an emitter region 9 and collector contact diffusion region 10. Contact holes are drilled in the silicon oxide film patterns 4a, 4b. Thus, an emitter electrode 11, base electrode 12 and collector electrode 13 are produced, in turn, producing a vertical npn type bipolar transistor (FIG. 1E). FIG. 2 is a plan view of the bipolar transistor of FIG. 1E.
In the aforementioned npn transistor, an element is isolated from the other elements by the field oxide films 7a, 7c having a thickness of about one micron and p type regions 6a, 6b. If, in the case, the n type silicon layer 3 is about as thin as 1 to 2 microns, the field oxide film can be brought into contact with the p type substrate 1 by selective oxidation. Therefore, the above-mentioned element isolation can be achieved only by said field oxide film. Even in this case, it is preferable to carry out the ion implantation of a p type impurity near the interface of the p type substrate and field oxide film for the formation of a channel-stopping region in order to suppress current leakage to the other element.
The above-mentioned process of isolating the npn bipolar transistor by the selective oxidation method has the following drawbacks:
(1) The isolation oxide films 7a, 7b, 7c defining the active regions (for example, the base region 8, emitter region 9) of an element have bird's beak-shaped end portions, and tend to undergo significant dimensional change, presenting difficulties in the communication of an element.
(2) For the formation of the p type impurity regions 6a, 6b, a mask has to be aligned with the oxide films 7a, 7b, 7c defining the active regions of an element, thereby obstructing integration.